OPC UA FX for constrained field devices. Targeting 8 kHz publishing over TSN, with a native realtime runtime and flexible configuration in Python or C++.
Bring OPC UA PubSub closer to the control loop. o6\FX separates cyclic execution from configuration so each part can run where it belongs.
8 kHz
Target publish frequency
TSN
IEEE 802.1AS clock synchronization and IEEE 802.1Qbv scheduled transmission
Hardware-vendor agnostic
Easy and proven portability
Low RAM footprint
<200 kB RAM for the realtime runtime. <500 kB RAM for the configuration runtime (OPC UA server).
8 kHz is the design target. Achievable rate and jitter depend on the hardware, workload, clock synchronization and network configuration, and require measurement on the target system.
Built on open62541, o6\FX combines the OPC UA FX information model with a separate native runtime for cyclic communication and application logic.
Python / C++
The implemented Automation Component and Connection Manager provide the foundation for device modeling and connection management. Use Python or C++ to configure your application and supervise Functional Entities outside the cyclic data path.
C11
An interrupt-driven bare-metal reference implementation provides the foundation for the C11 realtime runtime. It handles fixed-layout PubSub data and Functional Entity execution without dynamic allocation in the critical path.
The boundary between the two runtimes carries configuration and supervision. Cyclic process data stays in the native runtime.
Use bounded registries and configurable capacities to fit the runtime to your device. Map application variables directly into cyclic processing.
o6\FX supports IEEE 802.1AS clock synchronization and IEEE 802.1Qbv scheduled transmission over TSN. Align cyclic execution and network transmission to a shared clock.
Build on open62541 through o6\Python or o6-cpp. Select the variables, Functional Entities and PubSub groups that need native realtime execution.
Initial support is available for all major silicon vendors. The runtime separates its core logic from hardware-specific clock, timer and network interfaces, making it straightforward to port to different hardware targets and RTOS environments.
We participate in OPC Foundation and Avnu plugfests to test compatibility with other implementations and improve interoperability across devices and networks.
Tell us about your processor, memory budget, payload and TSN network. Together we can scope an integration and a measurement plan for your device.
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